The digital up/down converter products feature software programmable tuners that perform frequency translation and bandwidth reduction to achieve the desired signal characteristics. The hardware incorporates a rich set of software programmable features that include selectable operating modes (continuous, snapshot, periodic), external or timed event triggers, timestamped data samples, data sizing, and data packing. Data is sent to the host computer as a continuous stream of samples or in data packets defined by the VITA 49 specification.
Multiple products share a common code base with different analog-to-digital and digital-to-analog converter options for specific market needs. The analog interfaces can be either AC or DC coupled. The AC coupled configuration supports direct IF sampling (bandpass sampling) beyond the first Nyquist zone. The DC coupled option allows operating frequencies to approach zero without attenuation.
The products are available as a PCI Express mezzanine card (XMC), conduction cooled mezzanine card (CCXMC), or half-length PCI Express (PCIe) adapter card. The CCXMC can be mounted to any VITA 20-2001 compliant host without modification. All form factors offer four lane (x4) or eight lane (x8) bus operation at Gen 2 performance with backward compatibility to Gen1 and upward compatibility to Gen3. An optional user defined parallel bus is also available on the XMC P4 connector or a rear facing connector on the PCIe adapter.
The following is a list of current FPGA based DSP accelerator products with links to the corresponding datasheet.
|Model 271||Receiver||4 RX||16-bit||None||250 Msps||Gen2 (Gen1/Gen3 Compatible)|
|Model 273||Receiver||2 RX||16-bit||None||310 Msps||Gen2 (Gen1/Gen3 Compatible)|
|Model 277||Receiver||4 RX||16-bit||None||250 Msps||Gen2 (Gen1/Gen3 Compatible)|
Prior generations of analog/digital signal converter products are not listed here, but documentation and code can still be downloaded using the main menu above.